The present invention relates to a photomask for a double exposure process and a double exposure method using the same which enables a finer photoresist pattern to be formed through the double exposure process while minimizing yield reduction and cycle time due to misalignment of the photomask.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs.
Photolithography processes are commonly used in the manufacture of integrated circuits to create patterns within layers on a semiconductor wafer. As the complexity and circuit density of integrated circuits gradually increases, it has gradually become increasingly necessary to form patterns having a finer line width and a narrower line-spacing on semiconductor wafers. In order to achieve this task, a photoresist pattern formed in lithography processes is also required to have a finer line width and a narrower line-spacing corresponding to the pattern of the wafer.
However, due to the resolution limit caused by the diffraction of light in photolithography exposure process, it has been difficult to reduce the line width and line-spacing of the photoresist pattern below a certain level via a single exposure process. For this reason, various methods for forming a finer photoresist pattern through a modification in conventional exposure processes have been proposed.
In particular, a double exposure method has been proposed to form a photoresist pattern having a finer line width and a narrower line-spacing on a semiconductor wafer through separate exposure processes.
A conventional double exposure method and problems thereof will be described with reference to FIG. 1, which is a schematic view illustrating a conventional double exposure method.
Referring to FIG. 1, a first photomask 10 which has a first mask pattern 14, such as a first light shielding film pattern or a first phase shift film pattern formed on a first mask substrate 12 is provided. Second photomask 20 which has a second mask pattern 24, such as a second light shielding film pattern or a second phase shift film pattern formed on a second mask substrate 22 is additionally provided.
After first photomask 10 is disposed on a predetermined region of a semiconductor wafer on which a photoresist region to be patterned is formed, a primary exposure process is performed on the predetermined region of the semiconductor wafer using first mask pattern 14 formed on first photomask 10 as a mask.
Then, first photomask 10 is removed, and second photomask 20 is aligned to the predetermined region of the semiconductor wafer initially patterned by the primary exposure process. A secondary exposure process is then performed on the predetermined region of the semiconductor wafer using second mask pattern 24 formed on second photomask 20 as a mask.
First mask pattern 14 of first photomask 10 and second mask pattern 24 of second photomask 20 are formed to possess line widths and line-spacing so that the photoresist pattern can be desirably formed within the resolution limit by the current exposure process. The photoresist patterns corresponding to first mask pattern 14 and second photomask 20, respectively, are desirably formed on the predetermined region of the semiconductor wafer after the primary and secondary exposure processes are completed.
As a result, the photoresist patterns corresponding to first mask pattern 14 and second photomask 20, respectively, are formed together on the predetermined region of the semiconductor wafer processed by the double exposure method so that a photoresist pattern 32 having a very fine line width and line-spacing can be formed on a predetermined region 30 of the semiconductor wafer after the double exposure processes as shown in FIG. 1 (see the third pattern in FIG. 1).
Since the primary and secondary exposure processes are sequentially performed by separately using first photomask 10 and second photomask 20 in separate lithography processes, misalignment of first and second photomasks 10 and 20 can occur during alignment of first photomask 10 or second photomask 20 on the predetermined region of the semiconductor wafer. In this case, photoresist pattern 32 formed on predetermined region 30 of the semiconductor wafer can have an undesired line-spacing due to misalignment, leading to a defective photoresist pattern.
Since such a defective photoresist pattern often results in defective semiconductor devices, defective photoresist patterns are a major factor in the deterioration of yields in the manufacture of semiconductor device. In particular, as the line-spacing of the photoresist pattern on the semiconductor wafer becomes narrower, this problem is greatly exacerbated.
Furthermore, in the conventional double exposure method, other processes such as the removal of first photomask 10 and accurate alignment of second photomask 20 is performed after the primary exposure using first photomask 10 and before the second exposure process is begun, thereby reducing the yield of the double exposure process and the overall efficiency of the semiconductor device manufacturing process.